This project is funded by the 7th Framework Programme of the EC This project is funded by the 7th Framework Programme of the EC
The PARADIGM project is coordinated by COBRA The PARADIGM project is coordinated by COBRA

The JePPIX family: Inter-relationship between programmes EuroPIC and PARADIGM

PARADIGM and EuroPIC are FP7 funded research programmes which are related to the JePPIX platform initiative.

In Photonics, people have been working for several years towards commercial foundry activities for three different technologies, identified as the most important integration technologies by the FP6 Network of Excellence ePIXnet.  Together they cover a large part of the PIC applications space.

  • For Silicon based Application Specific Photonic Integrated Circuits (ASPICs) a foundry service already exists for passive optical components. IMEC, CEA-LETI and the University of Gent are running this service and organizing Multi-Project Wafer runs (MPW runs). HELIOS and WADIMOS are important European Projects working on further development of Silicon-based generic technology.
  • In the JePPIX consortium universities and companies are working together in a number of European and national projects on the development of a Generic Integration Platform technology for InP-based PICs which will lead to high-performance foundry processes for a broad field of applications. In the European projects EuroPIC and PARADIGM, Oclaro, the FhG Heinrich Hertz Institut are working on the development of foundry processes in InP for integration of both passive and active components.
  • The third Generic Integration Technology identified by the ePIXnet NoE is based on Si3N4 and SiO2 dielectric waveguide technology in the so-called TriPLEX platform, which supports passive and thermo optic components for operation through the whole wavelength range from visible to IR.

JePPIX stands for the Joint European Platform for InP-based Photonic Integration of Components and Circuits, in which the X stands for the two Cs (after flipping the first one). It was founded in 2007 by the FP6 Network of Excellence ePIXnet (the European Network in Photonic Integration of Components and Circuits) and is coordinated by the COBRA Research Institute from the TU Eindhoven.  After the expiration of ePIXnet in 2009 the JePPIX platform has been sustained at TU Eindhoven without external funding, but at a low activity level.  JePPIX has 14 partners, all key players in Photonics Integration: foundry and packaging partners (Oclaro, FhG-HHI, CIP), Photonic CAD companies (Phoenix, Photon Design and Filarete), Equipment manufacturers (ASML, Aixtron and Oxford Plasma Technologies) and a number of R&D institutes: Alcatel Thales III-V Lab, the University of Cambridge, Politecnico di Milano and the COBRA Research Institute of TU Eindhoven, who are coordinating the platform.  Further, JePPIX has a significant and rapidly growing number of users which are interested in participation in MPW runs in the short or longer term: at present more than 60 organisations (companies, universities, institutes, most of them in Europe, a few outside) have registered as JePPIX members.  For more information about the JePPIX platform go to:

JePPIX supports companies and universities in obtaining low-cost access to development and manufacturing of ASPICs.  This is done by providing and supporting pre-commercial access to the COBRA fab at TU/e, and in time, through a generic foundry processes that are presently being explored and developed in the EU-projects EuroPIC and PARADIGM.  Access is organised in a similar way as in microelectronics: Multi-Project Wafer (MPW) runs on standardized and well characterized processes with dedicated design kits, including component and sub-circuit libraries.  The concept of the MPW run has been pioneered in silicon electronics by the American MOSIS programme ( In Europe, a similar service model is applied by Europractice (

Europe has a clear lead in the development of a photonic foundry model, through EU projects like EuroPIC (InP Photonics), PARADIGM (InP photonics), HELIOS (Si Photonics) and WADIMOS (photonic interconnect on CMOS), and there are several related national research projects such as the Dutch project; MEMPHIS and the  Dutch IOP and STW funded research programmes.

Relationship between FP7 Project EuroPIC and PARADIGM

Many of the partners in PARADIGM are presently also conducting a project in the FP7 programme, EuroPIC European manufacturing platform for Photonic Integrated Circuits.· EuroPIC is primarily concerned with establishing a generic process in industry for the first time and with process extension to give real end–to-end coverage, “concept to PIC”.· PARADIGM is a much more technologically ambitious project than EuroPIC, aiming to introduce a second generation technology to the generic platform.

The Table below, may be helpful in explaining the relationship between the two projects.

Work package



Generic integration Technology

Optimisation, characterisation and validation of a 10GHz Tx platform and a 40GHz Rx platform. Limited funding for new technology development. Exploitation of existing technology

Development, characterization and validation of

a) 40GHz TxRx platform with extended functionality (polarization handling, modular gain blocks, SSC-array for I/O).

b) Extension of platform capability to new wavelength ranges (accessible by InP)

c) Use of a high isolation processes (e.g. SI substrates and ion implantation processes) for low parasitics and high integration levels.

d) Extension to BH active regions and SAG growth techniques for multi-wavelength circuits

Photonic CAD

Development of Models for Basic Building Blocks and layout tools

a) Development of a full photonic circuit simulator including layout tools.

b) Development of a design library at the component level, as well as the full range of building blocks provided by the new extended platforms

c) Attention to RF-design aspects

d) Attention to cross-talk issues

e) Design rule checking

Generic Packaging

Standardisation of optical and electrical I/O, carry out generic packaging trials.

Development of generic packaging approaches and developing prototype generic package(s) for a) low port count, b) close packed array I/O.

Generic Testing

Development of Generic Test algorithms and experimental setup for rapid testing and wafer validation

Design Capability

Consortium includes the EU’s first ASPIC design house – BB Photonics

Involve more universities in spinning out design expertise, move to create local design centres e.g. in the new member states.

Training and Education

Setting up photonic IC design and technology courses and educating users about application opportunities.


Sufficient to support project work-plan

Set up an organization with national contact points, for informing and supporting users and organizing training.