This project is funded by the 7th Framework Programme of the EC This project is funded by the 7th Framework Programme of the EC
The PARADIGM project is coordinated by COBRA The PARADIGM project is coordinated by COBRA

About Paradigm

PARADIGM Methodology

The strategy of the project is to pull down the barriers that currently prevent large-scale penetration of ASPICs in a broad range of applications. As the main barriers we have identified the absence of generic integration technologies that support a broad range of functionalities, the strong coupling between design and technology development, the absence of dedicated design kits and component libraries, the cost of qualifying individual components, rather than at a platform level, the absence of generic packaging technologies and the absence of a large market.  Our objectives are to lower these barriers such that we can effectively launch and demonstrate the generic integration paradigm for a number of pilot applications.  Central is the creation of design tools which contain knowledge of the processes involved, but PARADIGM also targets generic packaging as a major element of the generic foundry process line. 

Generic process flow from applications idea to product

PARADIGM aims to establish the technology and methodologies for highly accurate and reproducible manufacturing of high-reliability circuits. Accuracy will be achieved through the construction of high quality building block libraries, powerful design systems and extensive characterization. Reproducibility comes from well understood, stable processes and extensive manufacturing controls

PARADIGM also proposes to work towards platform-level qualification (analogous to capability approval in microelectronics) i.e. reach a situation where in any design that meets design rules should not require additional qualification with respect to reliability. This is a new concept in InP PIC manufacture.  Reliability and reproducibility are consistent themes throughout PARADIGM, where work is designed to set the stage for later commercialization including full product qualification.



Since 2007 JePPIX[1], has been brokering small-scale access to the Active-Passive integration process of the COBRA research institute of TU Eindhoven. The process supports integration of passive devices like couplers and arrayed waveguide grating multiplexers with active elements and represents the current state-of-the-art. However, the capability, reliability and performance of the experimental research platform, although excellent for proof-of-concept, are not adequate for the highly reproducible manufacturing required for commercial applications. The PARADIGM programme will establish the technology and methodologies needed for highly accurate and reproducible manufacturing of high-reliability circuits, also working towards platform-level qualification, a new concept in InP PIC manufacture.

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Generic Platform Technology Development: A breakthrough in Photonic Integration

Photonic Integrated Circuits (PICs) are considered as the way to make photonic systems or subsystems cheap and ubiquitous.  However, PICs still are several orders of magnitude more expensive than their microelectronic counterparts, and this has restricted their application to a few niche markets.  Paradigm targets a novel approach in photonic integration which will reduce the R&D costs of PICs by more than a factor of ten. It will bring the application of PICs that integrate complex and advanced photonic functionality on a single chip within reach for a large number of small and larger companies.  Europe presently has a world state-of-the-art position and is leading in this novel approach.

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How Generic Integration Technology Works

In Silicon micro-electronics a broad range of functionalities is realised from a rather small set of basic building blocks, like transistors, diodes, resistors, capacitors and interconnection tracks.  By connecting these building blocks in different numbers and topologies we can realize a huge variety of circuits and systems, with complexities ranging from a few hundred up to over a billion transistors.  In photonics we can actually do something similar.  On inspection of the functionality of a variety of optical circuits we see that most of them consist of a rather small set of components: lasers, optical amplifiers, modulators, detectors and passive components like couplers, filters and (de)multiplexers.  By proper design these components can be reduced to an even smaller set of basic building blocks.  In a generic integration technology that supports integration of the basic building blocks we can realize a variety of functionalities.

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The roadmap of microelectronics is focused on progress along the Moore’s law curve.  In Photonics we expect a different development.  It will start with commercial application of ASPICs with a complexity in the range of 5-50 components in rather basic generic foundry processes.  The next step will be an increase in performance and capabilities of the generic processes, e.g. with respect to speed, power consumption and number of basic building blocks supported, which may lead to some increase in the complexity of the chips, but not dramatic.  Once the foundry processes cover a wide range of applications, their steady performance improvement will allow for designing increasingly complex chips.

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